FIG. 14 is a circuit diagram illustrating a prior art differential amplifier having an input interface, for example, which is described in "Bipolar and MOS Analog Integrated Circuit design" written by Alan B. Grebene. In the figure, reference numeral 1 designates a first level shift circuit for dropping a DC voltage of an input signal D to a constant level, numeral 2 designates a second level shift circuit for dropping an input reference voltage V.sub.R by the same amount as in the first level shift circuit 1, and numeral 3 designates a differential amplifier that is connected directly or cascade-connected to the first and second level shift circuits 1 and 2 and is connected to the next stage through another level shift circuit (not shown).
In the first level shift circuit 1, reference numeral 4 designates a source follower field effect transistor (hereinafter referred to as an FET), numeral 5 designates a constant current source FET, numeral 6 designates a level shift diode comprising one diode or a plurality of diodes connected in series, and the anode electrode of the level shift diode 6 is connected to the source electrode of the source follower FET 4. The input signal D is input to the gate terminal of the source follower FET 4. The level shift diode 6 drops the DC voltage of the input signal D by an amount corresponding to a forward voltage that is produced due to a current supplied from the constant current source FET 5. For example, when a GaAs Schottky diode is employed as the diode, the amount of level shift is about 0.6 V per diode. In the second level shift circuit 2, reference numeral 7 designates a source follower FET, numeral 9 designates a constant current source FET, and numeral 8 designates a level shift diode comprising one diode or a plurality of diodes connected in series. Similarly, in the second level shift circuit 2, the input reference voltage V.sub.R is input to the gate terminal of the source follower FET 7, and it is dropped through the level shift diode 8 to be output.
In the differential amplifier 3, reference numerals 10 and 11 designate FETs serving as a source coupled transistor pair, and a high frequency signal is input to the gate of the FET 10 and a DC voltage is supplied to the gate of the FET 11. Reference numeral 12 designates a level shift diode for dropping a DC voltage of an output signal. Reference numerals 13 and 14 designate load resistors that are respectively connected in series to the drains of the FETs 10 and 11. Reference numeral 15 designates a constant current source that is connected to the sources of the FETs 10 and 11 constituting the source coupled transistor pair.
A description is given of the operation of the differential amplifier 3 utilizing signal waveforms shown in FIG. 15(a). At an arbitrary time T.sub.arb, the data signal V.sub.1, shown by a solid line in the figure, EQU V.sub.1 =V.sub.D +V.sub.D--PP,
is input to the gate electrode of the FET 10, and the phase inversion signal V.sub.2 shown by a dotted line in the figure, EQU V.sub.2 =V.sub.D -V.sub.D--PP,
is input to the gate terminal of the FET 11. The common-mode component V.sub.com and the differential component V.sub.dif included in common in two inputs of the differential amplifier 3 are defined as follows: EQU V.sub.com =(V.sub.1 +V.sub.2)/2=V.sub.D EQU V.sub.dif =(V.sub.1 -V.sub.2)/2=V.sub.D--PP
By using these equations, the input signals of the differential amplifier 3 can be expressed as: EQU V.sub.1 =V.sub.com +V.sub.dif EQU V.sub.2 =V.sub.com -V.sub.dif
The output voltage V.sub.OUT at the output OUT, a node between the FET 10 and the load resistor 13, and the output voltage V.sub./OUT at the output /OUT, serving as a node between the FET 11 and the load resistor 14, are represented by: ##EQU1## where Ad is the differential gain and Ac is the common-mode gain of the differential amplifier 3. Assuming that the difference .DELTA.V.sub.OUT between the output voltages at two output ends is an output, .DELTA.V.sub.OUT becomes: ##EQU2## Therefore, only the gain of the differential component can be obtained.
A description is given of the operation of the differential amplifier 3 when single end input as shown in FIG. 15(b). In the case of the single end input, the DC voltage V.sub.2 =V.sub.D (shown by a dotted line in the figure) is supplied to the gate terminal of the FET 11. The common-mode component V.sub.com and the differential component V.sub.dif are expressed as: EQU V.sub.com =(V.sub.1 +V.sub.2)/2=V.sub.D +V.sub.D--PP /2 EQU V.sub.dif =(V.sub.1 -V.sub.2)/2=V.sub.D--PP /2
In addition, the output voltages at the respective output ends are represented by: ##EQU3## The difference .DELTA.V.sub.OUT between the voltages becomes: ##EQU4##
Therefore, from the relationship between the amplitude V.sub.D--PP of the input signal V.sub.1 and the voltage difference .DELTA.V.sub.OUT, it is found that the gain for a single end input becomes 1/2 of the gain for a differential input. FIGS. 16(a)-16(c) are diagrams showing the relationship among input waveforms (FIG. 16(a)) and output waveforms (FIG. 16(b)) of the level shift circuits 1 and 2 and output waveforms (FIG. 16(c)) of the differential amplifier 3 at the single end input, with the time base as a reference. As is known from FIG. 16(b), in the single end input, since the input V.sub.R of the second level shift circuit 2 is a constant voltage, its output has a flat waveform reflecting the input.
In recent years, long-haul transmission has progressed in optical communication systems, and high-speed and high-sensitivity are demanded of optical transmitters-receivers used for the optical communication systems. An optical transmitter-receiver comprises a wideband amplifier, a dicision circuit for discriminating H level from L level of an input signal, and a driver for driving a laser diode, or the like. When transmission speed exceeding Gbps is required, these circuits are often constituted of differential amplifiers or source coupled type FET logics (SCFL), having an advantage of high speed. For example, in order to improve the input sensitivity of the decision circuit, it is necessary to increase the gain (differential gain Ad) of an input buffer comprising a differential amplifier. When differential signals, i.e., a data signal and a phase inversion signal, are input to two input terminals of the differential amplifier, the phase difference between the two inputs must be precisely adjusted. For that, it is required to adjust lengths of wirings which connect the signal sources and the inputs of the circuit, or to provide a phase adjusting circuit at one of the input terminals, so that the system design becomes complicated. Therefore, single end input is generally used. Consequently, although the gain should be increased, the gain is reduced by half because of the single end input.
More specifically, in the differential amplifier 3, the differential gain Ad is in proportion to transconductance gm of the source coupled FETs 10 and 11, and the resistance of the load resistors 13 and 14. Accordingly, in order to increase the gain, the transconductance gm, the resistance, or both of them may be increased. However, when an FET having a determined gate length is employed, the gate width of the FET must be increased in order to increase the transconductance gm, causing an increase in the gate-source capacitance or the gate-drain capacitance of the FET. Meanwhile, when the load resistance is increased, the CR time constant of the load resistance and the parasitic capacitance of the loads connected to the output ends, such as the input capacitance of the FETs connected to the outputs OUT and /OUT of the next stage, increases.
As a result, the increase in the transconductance gm or the resistance value causes band degradation, i.e., a reduction of the band in which a desired gain can be obtained, in a band where the input buffer is used. That is, as shown in FIG. 17, although a desired gain has usually been obtained up to a region of a frequency f, the desired gain is obtained only up to a region of a frequency f' lower than the frequency f. In addition, when the number of stages of differential amplifiers (input buffers) is increased in order to make the gain higher, the influence due to the band degradation described above becomes larger as the signal is transmitted from the amplifier of the previous stage to the amplifier of the next stage, whereby the band degradation is promoted and an increase in current is caused. Because of the above-described facts, it is difficult to make the gain higher by using a differential amplifier in optical transmitters-receivers for optical communication systems exceeding 10 Gbps, increasing the transconductance gm of the source coupled FETs constituting the differential amplifier and the resistance of the resistors connected in series to the respective source coupled FETs.
The prior art differential amplifier is constituted as described above, and the gain obtained with a single end input is below half of the gain for a differential input.